Samsung S3F401F - Manual (Page 202)

S3F401F_UM_REV1.00 SSP
10-1
10
SSP (SYNCHRONOUS SERIAL PORT)
1. OVERVIEW
The S3F401F has two channels’ synchronous communication interface, SSP0 and SSP1, based on the prime-cell
PL022 of ARM. The SSP is a master or slave interface that enables synchronous serial communication with slave or
master peripherals that have Motorola SPI. The transmit and receive paths are buffered with internal FIFO
memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial
data is transmitted on SSPTXD and received on SSPRXD. The SSP includes a programmable bit rate clock divider
and prescaler to generate the serial output clock SSPCLK from the input clock F
SSPCLK
. Bit rates are supported to
2MHz and higher, subject to choice of frequency for SSPCLK and the maximum bit rate is determined by peripheral
devices. The SSP operating mode, frame format, and size are programmed through the control registers SSPCR0
and SSPCR1. Depending on the selected operating mode, the SSPFSS output operates as an active LOW slave
select for SPI.
1.1 FEATURES
• Master or slave operation
• Programmable clock bit rate and pre-scale
• Separate transmit and receive first-in, first-out memory buffers, 16 bits wide, 8 locations deep.
• Programmable data frame size from 4 to 16 bits.
• Independent masking of transmit FIFO, receive FIFO, and receive overrun interrupts.
• Internal loop-back test mode is available.
1.2 PROGRAMMABLE PARAMETERS
The following parameters are programmable:
• Master or slave mode
• Enabling of operation
• Frame format
• Communication baud rate
• Clock phase and polarity
• Data widths from 4 to 16 bits wide
• Interrupt masking.