Samsung S3F401F - Manual (Page 192)

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00
9-4
2. PHASE LOCKED LOOP
2.1 PLL
The PLL within the clock generator is the circuit that synchronizes the output signal with a reference or input signal
in frequency as well as in phase. It is composed of the voltage controlled oscillator to generate the output frequency,
the divider P to divide the reference frequency by p, the divider M to divide the VCO output frequency by m, the
divider S to divide the VCO output frequency by s, the phase detector, charge pump, and loop filter. The output clock
frequency Fout is related to the reference input clock frequency Fin by the following equation:
Fpllo = (m * Fin) / (p * 2
s
)
m = M (the value for divider M) + 8, p = P (the value for divider P) + 2
The following sections describe the PLL operation that includes the phase detector, charge pump, VCO (Voltage
controlled oscillator), and loop filter.
Phase Detector
The phase detector monitors the phase difference between the Fref (the reference frequency) and Fvco (the output
frequency), and generates a control signal when it detects difference between the two.
Charge Pump
The charge pump converts the phase detector control signal to a charge in voltage across the external filter that
drives the VCO.
Loop Filter
The control signal that the phase detector generates for the charge pump may generate large excursions (ripples)
each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples
and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter
consisting of a resistor and capacitor.
A recommended external loop filter capacitance is 1200pF.
Voltage Controlled Oscillator (VCO)
The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease as a
function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the phase
detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter.
The VCO frequency then remains constant, and the PLL remains locked onto the system clock.