Samsung S3F401F - Manual (Page 203)

SSP S3F401F_UM_REV1.00
10-2
2. BLOCK DIAGRAM
Clock
Prescaler
Control
Unit
Transmit Shifter
Transmit FIFO
Register(16 bit x 8)
Transmitter
Receive FIFO
Register(16 bit x 8)
Receive Shifter
Receiver
Peripheral BUS
SSPTXn
PCLK
SSPRXn
Transmit Buffer Register
(Transmit FIFO)
Receive Buffer Register
(Receive FIFO)
SSPCLKn
SSPFSSn
Transmiter/
Receiver
Control Unit
Figure 10-1. SSP Block Diagram