CLOCK & POWER MANAGEMENT
S3F401F_UM_REV1.00
9-2
No
HIGH
SPEED
NORMAL
STOP
Yes
IDLE
SW
INT
CKFAIL
CM
RS
T
RESET
(any kind)
CM_PMSTAT.0
== 0
RST(*2)
RST (*1)
Figure 9-1. Clock State Machine Diagram
