Samsung S3F401F User Manual

Page 248

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UART

S3F401F_UM_REV1.00

12-10

3.7.1 IrDA Data Modulation

The IrDA SIR ENDEC comprises:

IrDA SIR transmit encoder

IrDA SIR receive decoder

The effect of IrDA 3/16 data modulation can be seen in next figure.

Bit period

Bit period

3

16

Stop

Bit

Start

Bit

Stop

Start

Data Bits

0

1

0

1

0

0

1

1

0

1

0

1

0

1

0

0

1

1

0

1

Data Bits

TXD

nSIROUT

SIRIN

RXD

Figure 12-3. IrDA data modulation

3.7.2 IrDA SIR Transmit Encoder

The SIR transmit encoder modulates the Non Return-to-Zero (NRZ) transmit bit stream output from the UART.
The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme that represents
logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver
and infrared Light Emitting Diode (LED).

In normal mode the transmitted pulse width is specified as three times the period of the internal x16 clock
(Baud16), that is, 3/16 of a bit period. In low-power mode the transmit pulse width is specified as 3/16 of a
115.2Kbits/s bit period. This is implemented as three times the period of a nominal 1.8432MHz clock
(IrLPBaud16) derived from dividing down of PCLK clock. The frequency of IrLPBaud16 is set up by writing the
appropriate divisor value to UARTILPR.

The active low encoder output is normally LOW for the marking state (no light pulse). The encoder outputs a high
pulse to generate an infrared light pulse representing a logic 0 or spacing state. In normal and low power IrDA
modes, when the fractional baud rate divider is used, the transmitted SIR pulse stream includes an increased
amount of jitter. This jitter is because the Baud16 pulses cannot be generated at regular intervals when fractional
division is used. That is, the Baud16 cycles have a different number of PCLK cycles. It can be shown that the
worst case jitter in the SIR pulse stream can be up to three PCLK cycles. This is within the limits of the SIR IrDA
Specification where the maximum amount of jitter allowed is 13%, as long as the PCLK is > 3.6864MHz and the
maximum baud rate used for normal mode SIR is <= 115.2 kbps. Under these conditions, the jitter is less than
9%.

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