Samsung S3F401F - Manual (Page 241)

S3F401F_UM_REV1.00 UART
12-3
1.3.2 IrDA SIR ENDEC block providing:
: Programmable use of IrDA SIR or UART input/output
: Support of IrDA SIR ENDEC functions for data rates up to 115.2Kbits/second half-duplex
: Support of normal 3/16 and low-power (1.41–2.23µs) bit durations
: Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode
bit duration.
• Identification registers that uniquely identify the UART. These can be used by an operating system to
automatically configure itself.
The S3F4101F UART (Universal Asynchronous Receiver and Transmitter) unit provides two independent
asynchronous serial I/O (SIO) ports, each of which can operate in interrupt-based or DMA-based mode. In other
words, UART can generate an interrupt or DMA request to transfer data between CPU and UART. It can support
bit rates of up to 115.2K bps. Each UART channel contains two 16-byte FIFOs for receive and transmit.
The S3F4101F UART includes programmable baud-rates, infra-red (IR) transmit/receive, one or two stop bit
insertion, 5-bit, 6-bit, 7-bit or 8-bit data width and parity checking.
Each UART contains a baud-rate generator, transmitter, receiver and control unit, as shown in Figure9-1. The
baud-rate generator can be clocked by PCLK. The transmitter and the receiver contain 16-byte FIFOs and data
shifters. Data, which is to be transmitted, is written to FIFO and then copied to the transmit shifter. It is then
shifted out by the transmit data pin (TxDn). The received data is shifted from the receive data pin (RxDn), and
then copied to FIFO from the shifter.
1.4 PROGRAMMABLE PARAMETERS
The following key parameters are programmable:
• Communication baud rate, integer, and fractional parts
• The number of data bits
• The number of stop bits
• Parity mode
• FIFO Enable (16 deep) or disable (1 deep)
• FIFO Trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8.
• Ιnternal nominal 1.8432MHz clock frequency (1.42–2.12MHz) to generate low-power mode shorter bit
duration