Samsung S3F401F - Manual (Page 128)

INTERRUPT CONTROLLER S3F401F_UM_REV1.00
7-4
2.2.3 Interrupt Mask Register (INTMSK)
The interrupt mask register has interrupt mask bits for all interrupt sources. When an interrupt source mask bit is
"0", the corresponding interrupt can not be serviced by the CPU when the corresponding interrupt request is
generated. If the mask bit is "1", the interrupt service can be done. Bit mapping of INTMSKn is same as
INTMODn.
Offset Addr Bit Name Description Reset Value
0x018
0x01C
0x020
xxx_MSK Each bit can disable or enable the corresponding interrupt
request.
0 = Interrupt service is masked or disabled.
1 = Interrupt service is available 0x0000_0000
2.2.4 INTOFFSIRQ Interrupt Offset Register for IRQ
The interrupt offset register, INTOFFSIRQ, contains the interrupt offset address of the interrupt source which has
the highest priority according to the interrupt priority setting among the pending interrupts.
2.2.5 INTOFFSFIQ INTERRUPT Offset Register for FIQ
The interrupt offset register, INTOFFSFIQ, contains the interrupt offset address of the interrupt source which has
the highest priority according to the interrupt priority setting among the pending interrupts.
2.2.6 INTIRQADDR INTERRUPT Vector Address Register for IRQ
The interrupt vector address register for IRQ, INTIRQADDR, contains the interrupt vector address of the IRQ
interrupt source which has the highest priority according to the interrupt priority setting among the pending
interrupts.
2.2.7 INTFIQADDR Interrupt Vector Address Register for FIQ
The interrupt vector address register for FIQ, INTFIQADDR, contains the interrupt vector address of the FIQ
interrupt source which has the highest priority according to the interrupt priority setting among the pending
interrupts.
2.2.8 Hardwired Vectored Interrupt Mode
If the interrupt latency is critical in the system, it is recommended to select the interrupt vector mode. Without time
latency of going through IRQ or FIQ base address to the real start address of respective interrupt source, it will
directly go to its base address matching to the request interrupt source. The below shows the fixed start address
of corresponding interrupt request when it has interrupt vector mode, nor normal interrupt mode.
When interrupt vector mode is enabled, the most high priority interrupt source among the interrupt request
occurrence is serviced by CPU. The CPU will branch into its vector address as shown below, directly.
When interrupt occurs, ARM core is forced from a fixed memory address by hardware. And Interrupts that we can
have are IRQ & FIQ.
− If IRQ interrupt occurs, the CPU jumps address [0x18].
− If FIQ interrupt occurs, the CPU jump address [0x1C].
− In other way PC’s value set 0x18 /0x1C.
In a vectored interrupt mode address is calculated with being based on IRQ or FIQ memory address. Because
ARM core is recognized all Interrupt Service Routine (ISR) address based on 0x18 or 0x1C. So direct ISR
address for user to make the H/W interrupt vector table has to be added.