Samsung S3F401F - Manual (Page 268)

UART S3F401F_UM_REV1.00
12-30
UART Raw Interrupt Status Register UARTRIS (0x03C) Access: Read Only
31 30 29 28 27 26 25 24
− − − − − − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23 22 21 20 19 18 17 16
− − − − − − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15 14 13 12 11 10 9 8
− − − − −
OERIS BERIS PERIS
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
FERIS RTRIS TXRIS RXRIS
− − − −
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
RXRIS Receive Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTRXINTR interrupt.
0: indicates UARTRXINTR interrupt is unmasked, enabled.
1: indicates UARTRXINTR interrupt is masked, disabled.
TXRIS Transmit Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTTXINTR interrupt.
RTRIS Receive Timeout Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTRTINTR interrupt.
FERIS Framing Error Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTFEINTR interrupt.
PERIS Parity Error Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTPEINTR interrupt.
BERIS Break Error Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTBEINTR interrupt.
OERIS Overrun Error Interrupt Status Bit
Gives the raw interrupt state (prior to masking) of the UARTOEINTR interrupt.
NOTE In this case the raw interrupt cannot be set unless the mask is set, this is because the mask acts as an
enable for power saving. That is, the same status can be read from UARTMIS and ARTRIS for the receive
timeout interrupt.