Samsung S3F401F - Manual (Page 247)

S3F401F_UM_REV1.00 UART
12-9
3.6.5 Disabling the FIFOs
Additionally, you can disable the FIFOs. In this case, the transmit and receive sides of the UART have 1-byte
holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received, and the
previous one was not yet read. In this implementation, the FIFOs are not physically disabled, but the flags are
manipulated to give the illusion of a 1-byte register. When the FIFOs are disabled, a write to the data register
bypasses the holding register unless the transmit shift register is already in use.
3.6.6 Loop-Back Mode
System and diagnostic
You can perform loopback testing for UART data by setting the Loop Back Enable (LBE) bit to 1 in the control
register UARTCR (bit 7). Data transmitted on UARTTXD is received on the UARTRXD input.
3.7 IrDA SIR OPERATION
The IrDA SIR ENDEC provides functionality that converts between an asynchronous UART data stream, and half-
duplex serial SIR interface. No analog processing is performed on-chip. The role of the SIR ENDEC is to provide
a digital encoded output, and decoded input to the UART. There are two modes of operation:
• In normal IrDA mode, a zero logic level is transmitted as high pulse of 3/ 16 th
duration of the selected baud
rate bit period on the nSIROUT signal, while logic one levels are transmitted as a static LOW signal. These
levels control the driver of an infrared transmitter, sending a pulse of light for each zero. On the reception
side, the incoming light pulses energize the photo transistor base of the receiver, pulling its output LOW. This
drives the SIRIN signal LOW.
• In low-power IrDA mode, the width of the transmitted infrared pulse is set to three times the period of the
internally generated IrLPBaud16 signal (1.63µs, assuming a nominal 1.8432MHz frequency) by changing the
appropriate bit in UARTCR.
In both normal and low-power IrDA modes:
• during transmission, the UART data bit is used as the base for encoding
• during reception, the decoded bits are transferred to the UART receive logic.
The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10ms delay between
transmission and reception. This delay must be generated by software because it is not supported by the UART.
The delay is required because the Infrared receiver electronics might become biased, or even saturated from the
optical power coupled from the adjacent transmitter LED. This delay is known as latency, or receiver setup time.
The IrLPBaud16 signal is generated by dividing down the PCLK signal according to the low-power divisor value
written to UARTILPR. The low-power divisor value is calculated as:
Low-power divisor = (F
PCLK
/ F
IrLPBaud16
)
where FIrLPBaud16 is nominally 1.8432MHz.
The divisor must be chosen so that 1.42MHz < F
IrLPBaud16
< 2.12MHz.