Samsung S3F401F - Manual (Page 210)

S3F401F_UM_REV1.00 SSP
10-9
2.2.3 SSP format with SPO=1, SPH=0
Single and continuous transmission signal sequences for SSP format with SPO=1, SPH=0 are shown in below
figure.
4 to 16 bits
SSPCLK
SSPFSS
SSPRXD Q LSB MSB
LSB MSB
SSPTXD
Figure 10-6. SSP frame format (single transfer) with SPO=1 and SPH=0
MSB
4 to 16 bits
SSPCLK
SSPFSS
SSPTXD/
SSPRXD
LSB MSB LSB
Figure 10-7. SSP frame format (continuous transfer) with SPO=1 and SPH=0
In this configuration, during idle periods
• The SSPCLK signal is forced HIGH
• SSPFSS is forced HIGH
• The transmit data line SSPTXD is arbitrarily forced LOW
• When the PrimeCell SSP is configured as a master, the SSPCLK is enabled.
• When the PrimeCell SSP is configured as a slave, the SSPCLK is disabled.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSS master signal being driven LOW, which causes slave data to be immediately transferred onto the SSPRXD
line of the master. The master SSPTXD output pad is enabled.
One half period later, valid master data is transferred to the SSPTXD line. Now that both the master and slave data
have been set, the SSPCLK master clock pin becomes LOW after one further half SSPCLK period. This means that
data is captured on the falling edges and be propagated on the rising edges of the SSPCLK signal.
In the case of a single word transmission, after all bits of the data word are transferred, the SSPFSS line is returned
to its idle HIGH state one SSPCLK period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSPFSS signal must be pulsed HIGH between
each data word transfer. This is because the slave select pin freezes the data in its serial peripheral register and
does not allow it to be altered if the SPH bit is logic zero. Therefore the master device must raise the SSPFSS pin of
the slave device between each data transfer to enable the serial peripheral data write. On completion of the
continuous transfer, the SSPFSS pin is returned to its idle state one SSPCLK period after the last bit has been
captured.