Samsung S3F401F - Manual (Page 127)

S3F401F_UM_REV1.00 INTERRUPT CONTROLLER
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2. FUNCTIONAL DESCRIPTION
The interrupt controller of S3F401F has the following features:
♦ The number of interrupt sources: 90
♦ Supports an IRQ and FIQ
♦ Configurable IRQ and FIQ services for each interrupt sources dynamically
♦ Programmable the priority of each service
♦ Supports a pending register for all interrupt sources, INTPND
♦ Supports an index register, INTOFFSIRQ, INTOFFSFIQ
♦ Supports a masking/unmasking feature, INTMSK
2.1 CONFIGURING IRQ AND FIQ INTERRUPT SERVICE
The S3F401F has its own interrupt sources and these interrupt sources must be configured to the FIQ and IRQ
interrupt services of the ARM processor (default value is set to IRQ). Each peripheral module generates interrupt
signal and this is transferred to the INTPND register. INTPND register hold each interrupt signals until it is
cleared. During INTPND register holds each interrupt signal these signals are transferred to the FIQ and IRQ
services depending on the INTMOD and INTMSK register. For more details of each register, refer to the each
register description.
2.2 INTERRUPT REGISTERS
2.2.1 Interrupt Mode Register
Each bit in INTMODn register can determine the interrupt mode of each interrupt request. In case of FIQ mode,
this bit should be ‘1’. Otherwise, it means the IRQ mode interrupt. The FIQ mode has higher priority than IRQ
mode. During the service of IRQ, the FIQ mode interrupt can occupy the CPU for its service.
2.2.2 Interrupt Pending Register
In CPU core, there is PSR (Processor Status Register) register, which has several fields including the interrupt
relating I-Flag and F-Flag. As mentioned above, the CPU accepts two kinds of interrupt even if there are many
interrupt sources in S3F401F. That is why all interrupt sources in S3F401F are categorized into two modes, which
are IRQ mode and FIQ mode. In this case, if CPU is running the service for a certain interrupt, and if this interrupt
has IRQ mode, the other interrupt sources with IRQ mode can not be serviced until the completion of current
service. These interrupts should be pending in INTPND (Interrupt Pending Register). In case of FIQ mode, other
FIQ interrupt request can not take CPU while the current FIQ service is running as same as IRQ case. Therefore,
the FIQ interrupt request should be pending in INTPND as same as IRQ. If IRQ interrupt service is running, the
FIQ interrupt can take the CPU for service because FIQ has higher priority than IRQ. In other word, ARM CPU
supports two level’s interrupt architecture. The pending interrupt service starts whenever the I-Flag or F-Flag is
cleared to ‘0’.The service routine should clear the pending bit, also. Bit mapping of INTPND is same as INTMOD.