Samsung S3F401F - Manual (Page 258)

UART S3F401F_UM_REV1.00
12-20
UART IrDA Low Counter Register UARTILPR (0x020) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
ILPDVSR[7:0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
ILPDVSR Low Power Divisor Value
The value for low-power divisor 8bits
NOTE Zero is an illegal value. Programming a zero value results in no IrLPBaud 16 pulses being generated.
IrDA LOW POWER COUNTER REGISTER (UARTILPR)
The UARTILPR register is the IrDA low-power counter register. This is an 8-bit read/write register that stores the
low-power counter divisor value used to generate the IrLPBaud16 signal by dividing down of PCLK. All the bits
are cleared to 0 when reset. If IrLPBaud16 signal is generated by dividing down the PCLK signal according to the
low-power divisor value written to UARTILPR.
The low-power divisor value is calculated as follows:
low-power divisor(ILPDVSR) = (F
PCLK
/ F
IrLPBaud16
)
where F
IrLPBaud16
is nominally 1.8432MHz.
You must choose the divisor so that 1.42MHz < F
IrLPBaud16
< 1.12MHz, that results in a low-power pulse duration of
1.41-2.11us (three times the period of IrLPBaud16).
The minimum frequency of IrLPBaud16 ensures that pulses less than one period of PCLK are rejected as random
noise, but that pulses greater than two periods of PCLK are accepted as valid pulse.