Samsung S3F401F - Manual (Page 200)

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00
9-12
PLL Locking Timer Register PLLLOCK (0x008) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
PLLLOCKIND[15:8]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1
7 6 5 4 3 2 1 0
PLLLOCKIND[7:0]
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
PLLLOCKIND PLL Locking Time End Compare Value
0x0000 ~ 0xFFFF
PMSTAT[5] is set to 1 if PLLLOCKIND is matched with PLL locking time counter(This register is
hidden for user.). PLL locking time counter with external clock is started when SYSCON[5] is set
to ‘1’. This register value must be set to appropriate value for 300us locking time. For example,
the external clock is 8MHz and PLLLOCKIND is set to 0x960, PMSTAT[5] is set to 1 after 300us.
(300us x 8MHz = 0x960) So, PLLLOCKIND must be set to value greater than 0x960 for 8MHz
external clock.