Samsung S3F401F - Manual (Page 211)

SSP S3F401F_UM_REV1.00
10-10
2.2.4 SSP Format with SPO=1, SPH=1
The transfer signal sequence for SSP format with SPO=1, SPH=1 is shown in below figure, which covers both single
and continuous transfers.
4 to 16 bits
SSPCLK
SSPFSS
SSPRXD Q LSB MSB
LSB MSB
SSPTXD
Q
Figure 10-8. SSP Frame Format with SPO=1 and SPH=1
In this configuration, during idle periods:
• The SSPCLK signal is forced HIGH
• SSPFSS is forced HIGH
• The transmit data line SSPTXD is arbitrarily forced LOW
• When the SSP is configured as a master, the SSPCLK is enabled.
• When the SSP is configured as a slave, the SSPCLK is disabled.
If the SSP is enabled and there is valid data within the transmit FIFO, the start of transmission is signified by the
SSPFSS master signal being driven LOW. The master SSPTXD output pad is enabled.
After a further one half SSPCLK period, both master and slave data are enabled onto their respective transmission
lines. At the same time, the SSPCLK is enabled with a falling edge transition. Data is then captured on the rising
edges and propagated on the falling edges of the SSPCLK signal.
After all bits have been transferred, in the case of a single word transmission, the SSPFSS line is returned to its idle
HIGH state one SSPCLK period after the last bit has been captured.
For continuous back-to-back transmissions, the SSPFSS pins remains in its active LOW state, until the final bit of
the last word has been captured, and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSPFSS pin is held LOW between successive data words and
termination is the same as that of the single word transfer.