Samsung S3F401F - Manual (Page 191)

S3F401F_UM_REV1.00 POWER MANAGEMENT
9-3
PCLK
M
U
X
Fin
Fpllo
SCLK
M
U
X
MCLK
ICLK
SYSCON.4: CLKSRC
SYSCON.5: PLLON
PLL
PMSTAT.0: CMRST
SYSCON.9-.8: PCLKDIV
SYSCON.3-.2: MCLKDIV SYSCON.1: IDLE
(peripherals)
(interrupt controller)
(CPU,Flash/SRAM)
Internal
Oscillator
Typ.1MHz
NOTES:
1. MCKL must be greater than PCLK.
2. PCLK,ICLK and MCLK can be slower than SCLK by PCLKDIV and MCLKDIV.
Clock
Divider
External
Oscillator
Clock
Divider
Figure 9-2. Clock Circuit Diagram