Samsung S3F401F - Manual (Page 205)

SSP S3F401F_UM_REV1.00
10-4
2.1.2 Clock Ratios
In the slave mode of operation, the SSPCLK pin signal from the external master is double synchronized and then
delayed to detect an edge. It takes three PCLKs to detect an edge on SSPCLK. SSPTXD has less setup time to the
falling edge of SSPCLK on which the master is sampling the line. The setup and hold times on SSPRXD with
reference to SSPCLK must be more conservative to ensure that it is at the right value when the actual sampling
occurs within the SSPMS. To ensure correct device operation, PCLK must be at least 12 times faster than the
maximum expected frequency of SSPCLK.
The frequency selected for PCLK must accommodate the desired range of bit clock rates. The ratio of minimum
PCLK frequency to SSPCLK maximum frequency in the case of the slave mode is 12 and for the master mode it is
two.
To generate a maximum bit rate of 1.8432Mbps in the Master mode, the frequency of PCLK must be at least
3.6864MHz. With an PCLK frequency of 3.6864MHz, the SSPCPSR register has to be programmed with a value of
two and the SCR[7:0] field in the SSPCR0 register needs to be programmed as zero.
To work with a maximum bit rate of 1.8432Mbps in the slave mode, the frequency of PCLK must be at least
22.12MHz. With an PCLK frequency of 22.12MHz, the SSPCPSR register can be programmed with a value of 12
and the SCR[7:0] field in the SSPCR0 register can be programmed as zero. Similarly the ratio of PCLK maximum
frequency to SSPCLK minimum frequency is 254 x 256. The minimum frequency of PCLK is governed by the
following equations, both of which have to be satisfied:
F
PCLK
(min) >= 2 x F
SSPCLK
(max) [for master mode]
F
PCLK
(min) >= 12 x F
SSPCLK
(max) [for slave mode].
The maximum frequency of PCLK is governed by the following equations, both of which have to be satisfied:
F
PCLK
(max) <= 254 x 256 x F
SSPCLK
(min) [for master mode]
F
PCLK
(max) <= 254 x 256 x F
SSPCLK
(min) [for slave mode]
Bit rate generation
The serial bit rate is derived by dividing down the input clock PCLK. The clock is first divided by an even pre-scale
value CPSDVSR from 2 to 254, which is programmed in SSPCPSR. The clock is further divided by a value from 1 to
256, which is 1 + SCR, where SCR is the value programmed in SSPCR0.
The frequency of the output signal bit clock SSPCLK is defined below:
F
SSPCLK
= F
PCLK
/ (CPSDVR x (1+SCR))
For example, if PCLK is 4MHz, and CPSDVSR = 2, then SSPCLK has a frequency range from 7.8KHz to 2MHz.