Samsung S3F401F - Manual (Page 220)

S3F401F_UM_REV1.00 SSP
10-19
Clock Prescale Register SSPCPSR (0x010) Access: Read/Write
31 30 29 28 27 26 25 24
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
− − − − − − − −
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
CPSDVSR[7:0]
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
CPSDVSR Clock Pre-scale Divisor Field
Must be an even number from 2 to 254, depending on the frequency of F
SSPCLK
. The least
significant bit always returns zero on reads.
NOTE SSPCPSR is the clock pre-scale register and specifies the division factor by which the input F
PCLK
must be internally divided before further use.
The value programmed into this register must be an even number between 2 to 254. The least
significant bit of the programmed number is hard-coded to zero. If an odd number is written to this
register, data read back from this register has the least significant bit as zero.