Samsung S3F401F - Manual (Page 230)

TIMER S3F401F_UM_REV1.00
11-6
2.4 PWM MODE OPERATION
The timer can be used for generating the PWM (Pulse Width Modulation) signal.
In this mode, a match signal should be generated when the counter value is identical to the written to the timer data
register. However, because the match signal dose not clear the counter, it can generate an overflow interrupt when
the counter value reaches to the TPDAT. After the overflow of counter value, the timer will count its value from
0x0000, again.
To generate the PWM signal, the PWM output should be "High" level as long as the counter value is less than(<) to
the value specified in Timer Buffer Register and "Low" level as long as the counter value is greater than or equal(> or
=) the value specified in Timer Buffer Register when TCON.1(IVT bit ) is equal to 0. Because it is 16-bit PWM timer,
the one period is equal to t
CLK
* (TPDAT+1).
One-shot PWM is supported also when OMS is equal to ‘111’. Only 1 cycle of PWM is generated. After 1 cycle, the
level of PWM is low regardless of TCON.1(IVT) value.
The pre-scale value can define the input clock frequency of Timer according to the following equation:
Timer input clock frequency (t
CLK
) = PCLK / (pre-scale value + 1)
pre-scale value = 0 - 255
Match
Clear
INTMASK
INTPND
TnOVF_PWM
TCLK
INT_TOFn
INTMASK
INTPND INT_TMCn
Match
TnCL
TnOVF_PWM
Match
TnCL
TnOVF_PWM
TCON.1: IVT
TnPWM
TnCL
Figure 11-5. Simplified Timer Function Diagram: PWM Mode