Samsung S3F401F - Manual (Page 140)

INTERRUPT CONTROLLER S3F401F_UM_REV1.00
7-16
INTERRUPT MASK1 Register INTMSK1 (0x01C) Access: Read/Write
31 30 29 28 27 26 25 24
PHASEZ1_MSK MAT_S1_MSK MAT_P1_MSK CAP_B1_MSK OVF_B1_MSK CAP_A1_MSK OVF_A1_MSK FAULT1_MSK
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23 22 21 20 19 18 17 16
ZERO1_MSK TOPCMP1_MSK ADCCMPF12_MSK ADCCMPR12_MSK ADCCMPF11_MSK ADCCMPR11_MSK ADCCMPF10_MSK ADCCMPR10_MSK
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15 14 13 12 11 10 9 8
PHASEZ0_MSK MAT_S0_MSK MAT_P0_MSK CAP_B0_MSK OVF_B0_MSK CAP_A0_MSK OVF_A0_MSK FAULT0_MSK
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
ZERO0_MSK TOPCMP0_MSK ADCCMPF02_MSK ADCCMPR02_MSK ADCCMPF01_MSK ADCCMPR01_MSK ADCCMPF00_MSK ADCCMPR00_MSK
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W: Write R: Read -0: 0 After reset -1: 1 After reset -U: Undefined after reset
Interrupt Mask Register 1
Each bit can disable or enable the corresponding interrupt request
0 = Interrupt service is masked or disabled.
INTMSK1
1 = Interrupt service is available.(Unmasked)
ADCCMPR00_MSK 0x0000_0001 ADCCMPR10_MSK 0x0001_0000
ADCCMPF00_MSK 0x0000_0002 ADCCMPF10_MSK 0x0002_0000
ADCCMPR01_MSK 0x0000_0004 ADCCMPR11_MSK 0x0004_0000
ADCCMPF01_MSK 0x0000_0008 ADCCMPF11_MSK 0x0008_0000
ADCCMPR02_MSK 0x0000_0010 ADCCMPR12_MSK 0x0010_0000
ADCCMPF02_MSK 0x0000_0020 ADCCMPF12_MSK 0x0020_0000
TOPCMP0_MSK 0x0000_0040 TOPCMP1_MSK 0x0040_0000
ZERO0_MSK 0x0000_0080 ZERO1_MSK 0x0080_0000
FAULT0_MSK 0x0000_0100 FAULT1_MSK 0x0100_0000
OVF_A0_MSK 0x0000_0200 OVF_A1_MSK 0x0200_0000
CAP_A0_MSK 0x0000_0400 CAP_A1_MSK 0x0400_0000
OVF_B0_MSK 0x0000_0800 OVF_B1_MSK 0x0800_0000
CAP_B0_MSK 0x0000_1000 CAP_B1_MSK 0x1000_0000
MAT_P0_MSK 0x0000_2000 MAT_P1_MSK 0x2000_0000
MAT_S0_MSK 0x0000_4000 MAT_S1_MSK 0x4000_0000
PHASEZ0_MSK 0x0000_8000 PHASEZ1_MSK 0x8000_0000