Samsung S3F401F - Manual (Page 207)

SSP S3F401F_UM_REV1.00
10-6
2.2 FRAME FORMAT
The frame format is programmed through the FRF bits and the data word size through the DSS bits. Bit phase and
polarity are programmed through the SPH and SPO bits.
The frame is between 4 and 16 bits long depending on the size of data programmed, and is transmitted starting with
the MSB.
The serial clock (SSPCLK) is held inactive while the SSP is idle, and transitions at the programmed frequency only
during active transmission or reception of data. The idle state of SSPCLK is utilized to provide a receive timeout
indication that occurs when the receive FIFO still contains data after a timeout period.
The serial frame (SSPFSS) pin is active LOW, and is asserted (pulled down) during the entire transmission of the
frame.
The SSP interface is a four-wire interface where the SSPFSS signal behaves as a slave select. The main feature of
the SSP format is that the inactive state and phase of the SSPCLK signal are programmable through the SPO and
SPH bits within the SSPSCR0 control register.
SPO: clock polarity
When the SPO clock polarity control bit is LOW, it produces a steady state low value on the SSPCLK. If the SPO
clock polarity control bit is HIGH, a steady state high value is placed on the SSPCLK when data is not being
transferred.
SPH: clock phase
The SPH control bit selects the clock edge that captures data and allows it to change state. It has the most impact on
the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
When the SPH phase control bit is LOW, data is captured on the first clock edge transition. If the SPH clock phase
control bit is HIGH, data is captured on the second clock edge transition.