Samsung S3F401F - Manual (Page 244)

UART S3F401F_UM_REV1.00
12-6
3. FUNCTION DESCRIPTION
3.1 BAUD RATE GENERATOR
The baud rate generator contains free-running counters that generate the internal x16 clocks, Baud16, and the
IrLPBaud16 signal. Baud16 provides timing information for UART transmit and receive control. Baud16 is a
stream of pulses with a width of one PCLK clock period and a frequency of 16 times the baud rate. IrLPBaud16
provides timing information to generate the pulse width of the IrDA encoded transmit bit stream when in low-
power mode.
3.1.1 Clock Signals
The frequency selected for PCLK must accommodate the desired range of baud rates:
PCLK (min) >= 16 x baud_rate (max)
PCLK (max) <= 16 x 65535 x baud_rate (min)
For example, for a range of baud rates from 110 baud to 460800 baud the PCLK frequency must be within the
range 7.3728MHz to 115MHz. The frequency of PCLK must also be within the required error limits for all baud
rates to be used.
3.1.2 Fractional Baud Rate Divider
The baud rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. This is used by
the baud rate generator to determine the bit period. The fractional baud rate divider enables the use of any clock
with a frequency >3.6864MHz to act as PCLK, while it is still possible to generate all the standard baud rates. The
16-bit integer is loaded through the UARTIBRD register. The 6-bit fractional part is loaded into the UARTFBRD
register. The Baud Rate Divisor has the following relationship to PCLK:
Baud Rate Divisor = PCLK/ (16xBaud Rate) = BRDI + BRDF
where BRDI is the integer part and BRDF is the fractional part separated by a decimal point
You can calculate the 6-bit number (m) by taking the fractional part of the required baud rate divisor and
multiplying it by 64 (that is, 2n, where n is the width of the UARTFBRD register) and adding 0.5 to account for
rounding errors:
m = integer (BRDF * 2n + 0.5)
An internal clock enable signal, Baud16, is generated, and is a stream of one PCLK wide pulses with an average
frequency of 16 times the desired baud rate. This signal is then divided by 16 to give the transmit clock. A low
number in the baud rate divisor gives a short bit period, and a high number in the baud rate divisor gives a long bit
period.