Samsung S3F401F - Manual (Page 214)

S3F401F_UM_REV1.00 SSP
10-13
2.3 INTERRUPT
There are five interrupts generated by the SSP. Four of these are individual and maskable:
Interrupt Description
SSPTXINTR SSP transmit FIFO service interrupt
SSPRXINTR SSP transmit FIFO service interrupt
SSPRORTINTR SSP receive overrun interrupt
SSPRTINTR SSP time out interrupt
2.3.1 Interrupt Generation Logic
The individual interrupt requests could also be used with a system interrupt controller that provides masking for the
outputs of each peripheral. In this way, a global interrupt controller service routine would be able to read the entire
set of sources from one wide register in the system interrupt controller. This is attractive where the time to read from
the peripheral registers is significant compared to the CPU clock speed in a real-time system.
Table 10-1. UART Interrupts In Connection With FIFO
Type FIFO Mode
TXINTR The transmit interrupt is asserted when there are four or less valid entries in the transmit FIFO.
The transmit interrupt SSPTXINTR is not qualified with the SSP enable signal, which allows
operation in one of two ways.
Data can be written to the transmit FIFO prior to enabling the PrimeCell SSP and interrupts.
Alternatively, the SSP and interrupts can be enabled so that data can be written to the transmit
FIFO by an interrupt service routine.
RXINTR The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.
OVERRUN
INTR
The receive overrun interrupt SSPORINTR is asserted when the FIFO is already full and an
additional data frame is received, causing an overrun of the FIFO. Data is over-written in the
receive shift register, but not the FIFO.
RECEIVE
TIMEOUT
INTR
The receive timeout interrupt is asserted when the receive FIFO is not empty and the PrimeCell
SSP has remained idle for a fixed 32 bit period. This mechanism ensures that the user is aware
that data is still present in the receive FIFO and requires servicing. This interrupt is deasserted if
the receive FIFO becomes empty by subsequent reads, or if new data is received on SSPRXD. It
can also be cleared by writing to the RTIC bit in the SSPICR register.
You can mask each of the four individual maskable interrupts by setting the appropriate bits in the SSPIMSC register.
Setting the appropriate mask bit HIGH enables the interrupt
Provision of the individual outputs as well as a combined interrupt output, allows use of either a global interrupt
service routine, or modular device drivers to handle interrupts.
The transmit and receive dynamic data-flow interrupts, SSPTXINTR and SSPRXINTR, are separated from the
status interrupts so that data can be read or written in response to the FIFO trigger levels.
The status of the individual interrupt sources can be read from SSPRIS and SSPMIS registers.