Samsung S3F401F - Manual (Page 194)

CLOCK & POWER MANAGEMENT S3F401F_UM_REV1.00
9-6
3. MODE CHANGE
3.1 CHANGING CLOCK SPEED FROM NORMAL MODE TO HIGHSPEED MODE [NORMAL Æ HIGHSPEED]
To change clock speed from normal to high speed mode, do the following steps.
1. Set the value of SYSPLLCON register.
2. Set SYSCON[5](PLLON) bit
3. Set the SYSCON[4] (CLKSRC) to change high speed mode after PLL stabilization time.
3.2 CHANGING CLOCK SPEED FROM HIGHSPEED MODE TO NORMAL MODE [HIGHSPEED
Æ NORMAL]
To change clock speed from high speed to normal speed mode, do the following steps.
1. Clear the SYSCON[4] (CLKSRC) to change normal speed mode
2. Clear SYSCON[5](PLLON) bit to disable PLL
3.3 ENTERING THE STOP MODE FROM HIGH SPEED MODE [HIGHSPEED Æ STOP]
To enter the stop mode, do the following steps.
1. Set CLKSRC=EXTCLK (STOP mode can be entered only from normal mode.)
2. Set the SYSCON[0](STOP)bit to enter the STOP mode.
3. There has to be at least 4xNOP instructions following the instruction to enter the STOP mode.
4. S3F401F is in STOP mode now.
IMPORTANT NOTE
STOP mode can be entered only from normal mode
3.4 EXIT FROM THE STOP MODE
To exit from the stop mode, the following steps should be executed. To configure the STOP exiting condition,
configure EINTMOD, EINTCON, INTMASK and SYSCON[7] registers. INT[30:0] will be issued to exit from the
STOP mode.
3.5 EXIT FROM THE CLOCK FAIL MODE
To exit from the clock fail mode, external reset or reset by watchdog timer can be used. PMSTAT[4] (CMSTAT)bit
can be used for external oscillator is not fail.
3.6 IDLE MODE AND INTERNAL FLASH ROM
In the IDLE mode, the internal flash ROM will be stopped together. Just after exiting the IDLE mode, the interval time
(32xMCLKs) for start-up time of the internal flash ROM should be available. This 32xMCLKs interval is inserted
automatically by H/W logic.
IMPORTANT NOTE
IDLE mode can be entered only from normal mode