Altera Arria V Avalon-ST - Manual (Page 110)

Bits Register Description
Reset
Value
Access
[1] When set, indicates a retry buffer uncorrectable ECC error.
0
RW1CS
[0] When set, indicates a RX buffer uncorrectable ECC error.
0
RW1CS
Correctable Internal Error Mask Register
Table 5-13: Correctable Internal Error Mask Register
The
Correctab le Internal Error Mask
register controls which errors are forwarded as Internal Correctable
Errors. This register is for debug only.
Bits Register Description Reset Value Access
[31:7] Reserved. 0 RO
[6] Mask for Corrected Internal Error reported by the Application
Layer.
1 RWS
[5] Mask for configuration error detected in CvP mode. 0 RWS
[4:2] Reserved. 0 RO
[1] Mask for retry buffer correctable ECC error. 1 RWS
[0] Mask for RX Buffer correctable ECC error. 1 RWS
Correctable Internal Error Status Register
Table 5-14: Correctable Internal Error Status Register
The
Correctable Internal Error Status
register reports the status of the internally checked errors that are
correctable. When these specific errors are enabled by the
Correctable Internal Error Mask
register, they are
forwarded as Correctable Internal Errors as defined in the PCI Express Base Specification 3.0. This register is for
debug only. It should only be used to observe behavior, not to drive logic custom logic.
Bits Register Description Reset Value Access
[31:6] Reserved. 0 RO
[5] When set, indicates a configuration error has been detected in
CvP mode which is reported as correctable. This bit is set
whenever a
CVP_CONFIG_ERROR
occurs while in
CVP_MODE
.
0 RW1CS
2014.12.15
Correctable Internal Error Mask Register 5-15
Registers Altera Corporation
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