Altera Arria V Avalon-ST - Manual (Page 95)

Test Signals
Table 4-25: Test Interface Signals
The
test_in
bus provides run-time control and monitoring of the internal state of the IP core.
Signal Direction Description
test_in[31:0] Input The bits of the
test_in
bus have the following definitions:
• [0]: Simulation mode. This signal can be set to 1 to accelerate
initialization by reducing the value of many initialization
counters.
• [1]: Reserved. Must be set to 1'b0.
• [2]: Descramble mode disable. This signal must be set to 1
during initialization in order to disable data scrambling. You
can use this bit in simulation for both Endpoints and Root
Ports to observe descrambled data on the link. Descrambled
data cannot be used in open systems because the link partner
typically scrambles the data.
• [4:3]: Reserved. Must be set to 4’b01.
• [5]: Compliance test mode. Disable/force compliance mode.
When set, prevents the LTSSM from entering compliance
mode. Toggling this bit controls the entry and exit from the
compliance state, enabling the transmission of compliance
patterns.
• [6]: Forces entry to compliance mode when a timeout is
reached in the polling.active state and not all lanes have
detected their exit condition.
• [7]: Disable low power state negotiation. Altera recommends
setting thist bit.
• [31:8] Reserved. Set to all 0s.
simu_mode_pipe Input
When high, indicates that the PIPE interface is in simulation
mode.
testin_zero Output When asserted, indicates accelerated initialization for simulation
is active.
4-58 Test Signals
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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