Altera Arria V Avalon-ST - Manual (Page 35)

Register Name Range Default Value Description
Class code 24 bits 0x00000000 Sets the read-only value of the
Class Code
register.
Address offset: 0x008.
Subsystem
Vendor ID
16 bits 0x00000000 Sets the read-only value of the
Subsystem Vendor ID
register in the PCI Type 0 Configuration Space. This
parameter cannot be set to 0xFFFF per the PCI Express
Base Specification. This value is assigned by PCI-SIG to
the device manufacturer. This register is only valid in
the Type 0 (Endpoint) Configuration Space.
Address offset: 0x02C.
Subsystem
Device ID
16 bits 0x00000000 Sets the read-only value of the
Subsystem Device ID
register in the PCI Type 0 Configuration Space.
Address offset: 0x02C
At run time, you can change the values of these registers using the optional reconfiguration block signals.
Related Information
PCI Express Base Specification 2.1 or 3.0
Func <n> Device
Table 3-11: Func <n> Device
Parameter Value Description
Function Level
Reset (FLR)
On/Off Turn On this option to set the Function Level Reset Capability
bit in the Device Capabilities register. This parameter applies
to Endpoints only.
Func <n> MSI and MSI-X Capabilities
Table 3-12: Func <n> MSI and MSI-X Capabilities
Parameter Value Description
MSI messages
requested
1, 2, 4, 8, 16, 32 Specifies the number of messages the Application Layer can
request. Sets the value of the
Multiple Message Capable
field of the
Message Control
register, 0x050[31:16].
MSI-X Capabilities
Implement MSI-
X
On/Off When On, enables the MSI-X functionality.
3-12 Func <n> Device
2014.12.15
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