Altera Arria V Avalon-ST - Manual (Page 9)

PCIe Link
PCIe Hard IP
RP
Switch
PCIe
Hard IP
RP
User Application
Logic
PCIe Hard IP
EP
PCIe Link PCIe Link
User Application
Logic
Altera FPGA with Hard IP for PCI Express
Altera FPGA with Hard IP for PCI Express
Active Serial or
Active Quad
Device Configuration
Configuration via Protocol (CvP)
using the PCI Express Link
Serial or
Quad Flash
USB
Download
cable
PCIe
Hard IP
EP
User
Application
Logic
Altera FPGA with Hard IP for PCI Express
Config
Control
CvP
USB
Host CPU
PCIe
Related Information
• Configuration via Protocol (CvP) on page 13-1
• Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide
Example Designs
Altera provides example designs to familiarize you with the available functionality. Each design connects
the device under test (DUT) to an application (APPS) as the figure below illustrates. Certain critical
parameters of the APPs component are set to match the values of DUT. If you change these parameters,
you must change the APPs component to match. You can change the values for all other parameters of
the DUT without editing the APPs component.
1-8 Example Designs
2014.12.15
Altera Corporation Datasheet
Send Feedback