Altera Arria V Avalon-ST User Manual
Page 173
The top-level of the testbench instantiates four main modules:
• <qsys_systemname>— This is the example Endpoint design. For more information about this module,
refer to Chaining DMA Design Examples.
• altpcietb_bfm_top_rp.v—This is the Root Port PCI Express BFM. For more information about this
module, refer to Root Port BFM.
• altpcietb_pipe_phy—There are eight instances of this module, one per lane. These modules intercon‐
nect the PIPE MAC layer interfaces of the Root Port and the Endpoint. The module mimics the
behavior of the PIPE PHY layer to both MAC interfaces.
• altpcietb_bfm_driver_chaining—This module drives transactions to the Root Port BFM. This is the
module that you modify to vary the transactions sent to the example Endpoint design or your own
design. For more information about this module, refer to Root Port Design Example.
In addition, the testbench has routines that perform the following tasks:
• Generates the reference clock for the Endpoint at the required frequency.
• Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the following parameters:
•
serial_sim_hwtcl
: Set this parameter in <instantiation name>_tb.v . This parameter controls
whether the testbench simulates in PIPE mode or serial mode. When is set to 0, the simulation
runs in PIPE mode; when set to 1, it runs in serial mode. Although the
serial_sim_hwtcl
parameter is available in other files, if you set this parameter at the lower level, then it will get
overwritten by the tb.v level.
•
serial_sim_hwtcl
: Set to 1 for serial simulation and 0 for PIPE simulation.
•
enable_pipe32_sim_hwtcl
: Set to 0 for serial simulation and 1 for PIPE simulation.
Related Information
•
Getting Started with the Arria V Hard IP for PCI Express
•
on page 16-4
•
•
on page 16-21
2014.12.15
Endpoint Testbench
16-3
Testbench and Design Example
Altera Corporation