Altera Arria V Avalon-ST - Manual (Page 228)

Related Information
BFM Log and Message Procedures on page 16-43
Debugging Simulations
You can modify the following default testbench parameter settings to facilitate debugging.
• For Gen1 and Gen2 variants, you can disable 8B/10B encoding and decoding by setting
test_in[2] =
1
in altpcietb_bfm_top_rp.v.
• You can view the most important PIPE interface signals,
txdata
,
txdatak
,
rxdata
, and
txdatak
at the
following level of the design hierarchy:
altpcie_<dev>_hip_pipen1b|
twentynm_hssi_<gen>_<lanes>_pcie_hip_rbc
.
16-58 Debugging Simulations
2014.12.15
Altera Corporation Testbench and Design Example
Send Feedback