Reset and clocks – Altera Arria V Avalon-ST User Manual
Page 112
Reset and Clocks
6
2014.12.15
The
pin_perst
signal from the input pin of the FPGA resets the Hard IP for PCI Express IP Core.
app_rstn
which resets the Application Layer logic is derived from
reset_status
and
pld_clk_inuse
,
which are outputs of the core. This reset controller is implemented in hardened logic. The figure below
provides a simplified view of the logic that implements the reset controller.
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