Top-level interfaces, Avalon-st interface, Clocks and reset – Altera Arria V Avalon-ST User Manual
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Related Information
Top-Level Interfaces
Avalon-ST Interface
An Avalon-ST interface connects the Application Layer and the Transaction Layer. This is a
point-to-point, streaming interface designed for high throughput applications. The Avalon-ST interface
includes the RX and TX datapaths.
For more information about the Avalon-ST interface, including timing diagrams, refer to the Avalon
Interface Specifications.
RX Datapath
The RX datapath transports data from the Transaction Layer to the Application Layer’s Avalon-ST
interface. Masking of non-posted requests is partially supported. Refer to the description of the
rx_st_mask
signal for further information about masking.
TX Datapath
The TX datapath transports data from the Application Layer's Avalon-ST interface to the Transaction
Layer. The Hard IP provides credit information to the Application Layer for posted headers, posted data,
non-posted headers, non-posted data, completion headers and completion data.
The Application Layer may track credits consumed and use the credit limit information to calculate the
number of credits available. However, to enforce the PCI Express Flow Control (FC) protocol, the Hard
IP also checks the available credits before sending a request to the link, and if the Application Layer
violates the available credits for a TLP it transmits, the Hard IP blocks that TLP and all future TLPs until
credits become available. By tracking the credit consumed information and calculating the credits
available, the Application Layer can optimize performance by selecting for transmission only the TLPs
that have credits available.
Related Information
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Clocks and Reset
The PCI Express Base Specification requires an input reference clock, which is called
refclk
in this design.
The PCI Express Base Specification stipulates that the frequency of this clock be 100 MHz.
The PCI Express Base Specification also requires a system configuration time of 100 ms. To meet this
specification, IP core includes an embedded hard reset controller. This reset controller exits the reset state
after the I/O ring of the device is initialized.
Related Information
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2014.12.15
Top-Level Interfaces
9-3
IP Core Architecture
Altera Corporation