Altera Arria V Avalon-ST User Manual
Page 155
Figure 10-1: Design Including Legacy PCI Buses Requiring Strong Ordering
Producer
PCI-toPCI Bridge
PCI Bus
Flag
Posted
Write Buffer
Consumer
PCI Bus
Memory
Read
Request
b. A shared memory architecture where more than one thread accesses the same locations in memory.
If either of these conditions exists, relaxed ordering will lead to incorrect results.
3. If your analysis determines that relaxed ordering does not lead to possible race conditions or read or
write hazards, you can enable relaxed ordering by setting the RO bit in the TLP header.
4. The following figure shows two PCIe Endpoints and Legacy Endpoint connected to a switch. The three
PCIe Endpoints are not likely to have data dependencies. Consequently, it would be safe to set the
relaxed ordering bit for devices connected to the switch. In this system, if relax ordering is not enabled,
a memory read to the legacy Endpoint is blocked. The legacy Endpoint read is blocked because an
earlier posted write cannot be completed as the write buffer is full. .
10-10
Using Relaxed Ordering
2014.12.15
Altera Corporation
Transaction Layer Protocol (TLP) Details