Altera Arria V Avalon-ST - Manual (Page 43)

Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
To facilitate the interface to 64-bit memories, the Arria V Hard IP for PCI Express aligns data to the
qword or 64 bits by default. Consequently, if the header presents an address that is not qword aligned, the
Hard IP block shifts the data within the qword to achieve the correct alignment.
Qword alignment applies to all types of request TLPs with data, including the following TLPs:
• Memory writes
• Configuration writes
• I/O writes
The alignment of the request TLP depends on bit 2 of the request address. For completion TLPs with data,
alignment depends on bit 2 of the
lower address
field. This bit is always 0 (aligned to qword boundary)
for completion with data TLPs that are for configuration read or I/O read requests.
Figure 4-2: Qword Alignment
The following figure shows how an address that is not qword aligned, 0x4, is stored in memory. The byte
enables only qualify data that is being written. This means that the byte enables are undefined for 0x0–
0x3. This example corresponds to 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header
TLPs with Non-Qword Aligned Address.
.
.
.
0x0
0x8
0x10
0x18
Header Addr = 0x4
64 bits
PCB Memory
Valid Data
Valid Data
The following table shows the byte ordering for header and data packets.
Table 4-3: Mapping Avalon-ST Packets to PCI Express TLPs
Packet TLP
Header0 pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3
Header1 pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7
Header2 pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11
Header3 pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15
Data0 pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0
4-6 Data Alignment and Timing for the 64‑Bit Avalon‑ST RX Interface
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
Send Feedback