Altera Arria V Avalon-ST - Manual (Page 57)

Figure 4-19: 64-Bit Back-to-Back Transmission on the TX Interface
The following figure illustrates back-to-back transmission of 64-bit packets with no idle cycles between
the assertion of
tx_st_eop
and
tx_st_sop
.
coreclkout
tx_st_sop
tx_st_eop
tx_st_ready
tx_st_valid
tx_st_err
tx_st_data[63:0] 01 ... 00 ... BB ... BB ... BB ... BB ... B ... ... BB ... 01 ... 00 ... CC ... CC ... CC ... CC ... CC ... CC ...
Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
Figure 4-20: 128-Bit Avalon-ST tx_st_data Cycle Definition for 3-Dword Header TLP with Qword
Aligned Address
The following figure shows the mapping of 128-bit Avalon-ST TX packets to PCI Express TLPs for a three
dword header with qword aligned addresses. Assertion of
tx_st_empty
in an
rx_st_eop
cycle indicates
valid data in the lower 64 bits of
tx_st_data
.
Data3
Header2 Data 2
Header1 Data1 Data(n)
Header0 Data0 Data(n-1)
pld_clk
tx_st_valid
tx_st_data[127:96]
tx_st_data[95:64]
tx_st_data[63:32]
tx_st_data[31:0]
tx_st_sop
tx_st_eop
tx_st_empty
4-20 Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface
2014.12.15
Altera Corporation Interfaces and Signal Descriptions
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