Altera Arria V Avalon-ST - Manual (Page 86)

Serial Interface Signals
Table 4-21: Serial Interface Signals
In the following table, <n> = 1, 2, 4, or 8.
Signal Direction Description
tx_out[<n>-1:0]
Output Transmit input. These signals are the serial outputs.
rx_in[<n>-1:0]
Input Receive input. These signals are the serial inputs.
Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls
formats.
Related Information
Pin-out Files for Altera Devices
Physical Layout of Hard IP in Arria V Devices
/>Arria V devices include one or two Hard IP for PCI Express IP cores. The following figures illustrate the
placement of the PCIe IP cores, transceiver banks, and channels. Note that the bottom left IP core
includes the CvP functionality. The other Hard IP blocks do not include the CvP functionality.
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side
of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the
device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the
left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files
for Altera Devices.
2014.12.15
Serial Interface Signals 4-49
Interfaces and Signal Descriptions Altera Corporation
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