Altera Arria V Avalon-ST User Manual
Page 14
Getting Started with the Arria V Hard IP for PCI
Express
2
2014.12.15
This section provides instructions to help you quickly customize, simulate, and compile the Arria V Hard
IP for PCI Express IP Core. When you install the Quartus II software you also install the IP Library. This
installation includes design examples for Hard IP for PCI Express under the
<install_dir>/ip/altera/altera_
pcie/
directory.
After you install the Quartus II software for 14.0, you can copy the design examples from the
<install_dir>/
ip/altera/altera_pcie/altera_pcie/altera_pcie_hip_ast_ed/example_designs/<dev>
directory. This walkthrough
uses the Gen1 ×4 Endpoint, pcie_de_gen1_x4_ast64.qsys. The following figure illustrates the top-level
modules of the testbench in which the DUT, a Gen1 Endpoint, connects to a chaining DMA engine,
labeled APPS in the following figure, and a Root Port model. The simulation can use the parallel PHY
Interface for PCI Express (PIPE) or serial interface.
Figure 2-1: Testbench for an Endpoint
APPS
altpcied_<dev>_hwtcl.v
Hard IP for PCI Express Testbench for Endpoints
Avalon-ST TX
Avalon-ST RX
reset
status
Avalon-ST TX
Avalon-ST RX
reset
status
DUT
altpcie_<dev>_hip_ast_hwtcl.v
Root Port Model
altpcie_tbed_<dev>_hwtcl.v
PIPE or
Serial
Interface
Root Port BFM
altpcietb_bfm_rpvar_64b_x8_pipen1b
Root Port Driver and Monitor
altpcietb_bfm_vc_intf
Altera provides example designs to help you get started with the Arria V Hard IP for PCI Express IP Core.
You can use example designs as a starting point for your own design. The example designs include scripts
to compile and simulate the Arria V Hard IP for PCI Express IP Core. This example design provides a
simple method to perform basic testing of the Application Layer logic that interfaces to the Hard IP for
PCI Express.
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