Interrupts, Interrupts for endpoints, Msi interrupts – Altera Arria V Avalon-ST User Manual
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Interrupts
7
2014.12.15
Interrupts for Endpoints
The Arria V Hard IP for PCI Express provides support for PCI Express MSI, MSI-X, and legacy interrupts
when configured in Endpoint mode. The MSI, MSI-X, and legacy interrupts are mutually exclusive. After
power up, the Hard IP block starts in legacy interrupt mode, after which time software decides whether to
switch to MSI mode by programming the
msi_enable
bit of the
MSI Message Control Register
,
(bit[16] of 0x050) to 1, or to MSI-X mode if you turn on Implement MSI-X under the PCI Express/PCI
Capabilities tab using the parameter editor. If you turn on the Implement MSI-X option, you should
implement the MSI-X table structures at the memory space pointed to by the BARs.
Refer to section 6.1 of PCI Express Base Specification for a general description of PCI Express interrupt
support for Endpoints.
Related Information
MSI Interrupts
MSI interrupts are signaled on the PCI Express link using a single dword memory write TLP generated
internally by the Arria V Hard IP for PCI Express. The
app_msi_req
input port controls MSI interrupt
generation. When the input port asserts
app_msi_req
, it causes a MSI posted write TLP to be generated
based on the MSI configuration register values and the
app_msi_tc
(traffic class) and
app_msi_num
(number) input ports. To enable MSI interrupts, software must first set the
MSI enable
bit and then
disable legacy interrupts by setting the
Interrupt Disable
which is bit 10 of the
Command
register.
The following figure illustrates the architecture of the MSI handler block.
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