Altera Arria V Avalon-ST - Manual (Page 153)

• A Memory Write or Message Request with the Relaxed Ordering Attribute bit clear (b’0) must not pass
any other Memory Write or Message Request.
• A Memory Write or Message Request with the Relaxed Ordering Attribute bit set (b’1) is permitted to
pass any other Memory Write or Message Request.
• Endpoints, Switches, and Root Complex may allow Memory Write and Message Requests to pass
Completions or be blocked by Completions.
• Memory Write and Message Requests can pass Completions traveling in the PCI Express to PCI
directions to avoid deadlock.
• If the Relaxed Ordering attribute is not set, then a Read Completion cannot pass a previously
enqueued Memory Write or Message Request.
• If the Relaxed Ordering attribute is set, then a Read Completion is permitted to pass a previously
enqueued Memory Write or Message Request.
• Read Completion associated with different Read Requests are allowed to be blocked by or to pass each
other.
• Read Completions for Request (same Transaction ID) must return in address order.
• Non-posted requests cannot pass other non-posted requests.
•
CfgRd0
CfgRd0 can pass
IORd
or
MRd
.
•
CfgWr0
can
IORd
or
MRd
.
•
CfgRd0
can pass
IORd
or
MRd
.
•
CfrWr0
can pass
IOWr
.
Table 10-8: Transaction Ordering Rules
Can the Row Pass
the Column?
Posted Req Non Posted Req
Completion
Memory Write or
Message Req
Read Request I/O or Cfg Write Req
Spec Hard IP Spec Hard IP Spec Hard IP Spec Hard IP
P Posted
Req
No
Y/N No
No Yes Yes Yes Yes Y/N
Yes No
No
NP
Read
Req
No No Y/N No Y/N No Y/N No
Non-
Posted
Req with
data
No No Y/N No Y/N No Y/N No
10-8 Receive Buffer Reordering
2014.12.15
Altera Corporation Transaction Layer Protocol (TLP) Details
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