Altera Arria V Avalon-ST - Manual (Page 175)

The end point or Root Port variant is generated in the language (Verilog HDL or VHDL) that you selected
for the variation file. The testbench files are only generated in Verilog HDL in the current release. If you
choose to use VHDL for your variant, you must have a mixed-language simulator to run this testbench.
Note: The chaining DMA design example requires setting BAR 2 or BAR 3 to a minimum of 256 bytes.
To run the DMA tests using MSI, you must set the Number of MSI messages requested parameter
under the PCI Express/PCI Capabilities page to at least 2.
The chaining DMA design example uses an architecture capable of transferring a large amount of
fragmented memory without accessing the DMA registers for every memory block. For each block of
memory to be transferred, the chaining DMA design example uses a descriptor table containing the
following information:
• Length of the transfer
• Address of the source
• Address of the destination
• Control bits to set the handshaking behavior between the software application or BFM driver and the
chaining DMA module
Note: The chaining DMA design example only supports dword-aligned accesses. The chaining DMA
design example does not support ECRC forwarding.
The BFM driver writes the descriptor tables into BFM shared memory, from which the chaining DMA
design engine continuously collects the descriptor tables for DMA read, DMA write, or both. At the
beginning of the transfer, the BFM programs the Endpoint chaining DMA control register. The chaining
DMA control register indicates the total number of descriptor tables and the BFM shared memory
address of the first descriptor table. After programming the chaining DMA control register, the chaining
DMA engine continuously fetches descriptors from the BFM shared memory for both DMA reads and
DMA writes, and then performs the data transfer for each descriptor.
The following figure shows a block diagram of the design example connected to an external RC CPU. For
a description of the DMA write and read registers, Chaining DMA Control and Status Registers.
2014.12.15
Chaining DMA Design Examples 16-5
Testbench and Design Example Altera Corporation
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