Altera Arria V Avalon-ST - Manual (Page 177)

The following modules are included in the design example and located in the subdirectory
<qsys_systemname>/testbench/<qsys_system_name>_tb/simulation/submodules :
• <qsys_systemname> —This module is the top level of the example Endpoint design that you use for
simulation.
This module provides both PIPE and serial interfaces for the simulation environment. This module
has a
test_in
debug ports. Refer to Test Signalswhich allow you to monitor and control internal states
of the Hard IP.
For synthesis, the top level module is
<qsys_systemname>/synthesis/submodules . This module instantiates
the top-level module and propagates only a small sub-set of the test ports to the external I/Os. These
test ports can be used in your design.
• <variation name>.v or <variation name>.vhd— Because Altera provides five sample parameteriza‐
tions, you may have to edit one of the provided examples to create a simulation that matches your
requirements. <variation name>.v or <variation name>.vhd— Because Altera provides five sample
parameterizations, you may have to edit one of the provided examples to create a simulation that
matches your requirements.
The chaining DMA design example hierarchy consists of these components:
• A DMA read and a DMA write module
• An on-chip Endpoint memory (Avalon-MM slave) which uses two Avalon-MM interfaces for each
engine
The RC slave module is used primarily for downstream transactions which target the Endpoint on-chip
buffer memory. These target memory transactions bypass the DMA engines. In addition, the RC slave
module monitors performance and acknowledges incoming message TLPs. Each DMA module consists of
these components:
• Control register module—The RC programs the control register (four dwords) to start the DMA.
• Descriptor module—The DMA engine fetches four dword descriptors from BFM shared memory
which hosts the chaining DMA descriptor table.
• Requester module—For a given descriptor, the DMA engine performs the memory transfer between
Endpoint memory and the BFM shared memory.
2014.12.15
Chaining DMA Design Examples 16-7
Testbench and Design Example Altera Corporation
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