Receive buffer reordering – Altera Arria V Avalon-ST User Manual
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• The Type 0 Configuration TLPs are only routed to the Configuration Space of the Hard IP and are not
sent downstream on the PCI Express link.
• The Type 1 Configuration TLPs are sent downstream on the PCI Express link. If the bus number of the
Type 1 Configuration TLP matches the Secondary Bus Number register value in the Root Port
Configuration Space, the TLP is converted to a Type 0 TLP.
• For more information about routing rules in Root Port mode, refer to Section 7.3.3 Configuration
Request Routing Rules in the PCI Express Base Specification .
Related Information
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Receive Buffer Reordering
The PCI, PCI-X and PCI Express protocols include ordering rules for concurrent TLPs. Ordering rules
are necessary for the following reasons:
• To guarantee that TLPs complete in the intended order
• To avoid deadlock
• To maintain computability with ordering used on legacy buses
• To maximize performance and throughput by minimizing read latencies and managing read/write
ordering
• To avoid race conditions in systems that include legacy PCI buses by guaranteeing that reads to an
address do not complete before an earlier write to the same address
PCI uses a strongly-ordered model with some exceptions to avoid potential deadlock conditions. PCI-X
added a relaxed ordering (RO) bit in the TLP header. It is bit 5 of byte 2 in the TLP header, or the high-
order bit of the
attributes
field in the TLP formats shown in Chapter A, Transaction Layer Packet
(TLP) Header Formats. If this bit is set, relaxed ordering is permitted. If software can guarantee that no
dependencies exist between pending transactions, you can safely set the relaxed ordering bit.
The following table summarizes the ordering rules from the PCI specification. In this table, the entries
have the following meanings:
• Columns represent the first transaction issued.
• Rows represent the next transaction.
• At each intersection, the implicit question is: should this row packet be allowed to pass the column
packet? The following three answers are possible:
• Yes: the second transaction must be allowed to pass the first to avoid deadlock.
• Y/N: There are no requirements. A device may allow the second transaction to pass the first.
• No: The second transaction must not be allowed to pass the first.
The following transaction ordering rules apply to the table below.
2014.12.15
Receive Buffer Reordering
10-7
Transaction Layer Protocol (TLP) Details
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