Altera Quartus II Scripting - Manual (Page 114)

2–88 Chapter 2: Command-line Executables
quartus_tan
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
--check_constraints[=<setup|hold|both>]
Option to check unconstrained keeper to keeper pairs (unconstrained paths) in the design. Results are
reported in the Quartus Report Panel and ASCII format.
Optional argument can take value of:
setup: Perform setup analysis.
hold: Perform hold analysis.
both: Perform both setup and hold analysis. Default.
Examples
# Example 1. Check clock setup and hold time unconstrained paths on
# project chiptrip revision chiptrip.
quartus_tan chiptrip -c chiptrip --check_constraints
# Example 2. Check clock hold time unconstrained paths on project chiptrip.
# Force reporting results even the design is largely unconstrained.
quartus_tan chiptrip --check_constraints=hold
--combined_model[=on|off]
Option to run Timing Analyzer using both minimum delays and maximum delays, producing reports for
both.
--create_timing_netlist
Create and save a timing netlist to disk.
Example
execute_module -tool tan -args "--create_timing_netlist"
load_package advanced_timing
project_open chiptrip
read_timing_netlist
foreach_in_collection node [get_timing_nodes -type all] {
set type [get_timing_node_info -info type $node]
set name [get_timing_node_info -info name $node]
puts "$node => $type <=> $name"
}
--datasheet[=<output file name>]
Generates the actual delay timing datasheet for both Stratix and HardCopy revisions using the optionally
specified output file name reporting the. By default, the command uses <revision>.datasheet.txt if you do
not specify an output file name.
--delay_annotation_only
Option to run only delay annotation and skip full timing analysis. This option can be used when you use a
third-party timing analyzer or when you run timing simulation without timing analysis.
Example
quartus_tan top --delay_annotation_only
quartus_sim top --mode=timing
quartus_eda top --timing_analysis --tool=primetime --format=verilog