Altera Quartus II Scripting - Manual (Page 412)

3–282 Chapter 3: Tcl Packages & Commands
sdc
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
sdc
Synopsys Design Constraint (SDC) format is used to specify the design intent, including the timing and
area constraints of the design. The TimeQuest Timing Analyzer only implements the set of SDC
commands required to specify the timing constraints of the design. For area constraints, the QSF file
should be used.
This package implements the SDC Spec Version 1.5 (June 2005).
Any command in this package can be specified in a TimeQuest SDC file.
This package is loaded by default in the following executable:
■ quartus_sta
This package is available for loading in the following executable:
■ quartus_map
This package includes the following commands:
Command Page
all_clocks ............................................................................................................................................... 3–283
all_inputs............................................................................................................................................... 3–284
all_outputs ............................................................................................................................................ 3–285
all_registers ........................................................................................................................................... 3–286
create_clock........................................................................................................................................... 3–287
create_generated_clock ....................................................................................................................... 3–288
derive_clocks ........................................................................................................................................ 3–290
get_cells ................................................................................................................................................. 3–291
get_clocks .............................................................................................................................................. 3–293
get_nets.................................................................................................................................................. 3–294
get_pins ................................................................................................................................................. 3–295
get_ports................................................................................................................................................ 3–297
remove_clock_groups ......................................................................................................................... 3–298
remove_clock_latency ......................................................................................................................... 3–299
remove_clock_uncertainty.................................................................................................................. 3–300
remove_disable_timing....................................................................................................................... 3–301
remove_input_delay............................................................................................................................ 3–302
remove_output_delay ......................................................................................................................... 3–303
reset_design .......................................................................................................................................... 3–304
set_clock_groups .................................................................................................................................. 3–305
set_clock_latency.................................................................................................................................. 3–306
set_clock_uncertainty .......................................................................................................................... 3–308
set_disable_timing ............................................................................................................................... 3–309
set_false_path ....................................................................................................................................... 3–310
set_input_delay .................................................................................................................................... 3–312
set_input_transition............................................................................................................................. 3–314
set_max_delay ...................................................................................................................................... 3–315
set_min_delay....................................................................................................................................... 3–317
set_multicycle_path ............................................................................................................................. 3–319
set_output_delay.................................................................................................................................. 3–321