Altera Quartus II Scripting - Manual (Page 508)

3–378 Chapter 3: Tcl Packages & Commands
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Quartus II Scripting Reference Manual © July 2013 Altera Corporation
The loops check verifies that there are no strongly connected components in the netlist. These loops
prevent a design from being properly analyzed. The loops check also reports if loops exist but were
marked so that they would not be traversed.
The latches check reports latches in the design and warns that latches may not be analyzed properly. For
best results, change your design to remove latches whenever possible.
The pos_neg_clock_domain check determines if any register is clocked by both the rising and falling edges
of the same clock. If this scenario is necessary such as in a clock multiplexer, create two separate clocks that
have similar settings and are assigned to the same node.
The pll_cross_check checks the clocks that are assigned to a PLL against the PLL settings defined in design
files. Inconsistent settings or an unmatched number of clocks associated with the PLL are reported to the
user.
The uncertainty check reports each clock-to-clock transfer that does not have a clock uncertainty
assignment set between the two clocks. When a device family has derive_clock_uncertainty support, this
report also checks if a user-defined set_clock_uncertainty assignment has a less than recommended clock
uncertainty value.
The virtual_clock check reports all unreferenced virtual clocks. It also reports if design does not have any
virtual clock assignment.
The partial_multicycle check ensures that each setup multicycle assignment has a corresponding hold
multicycle assignment, and each hold muticycle assignment has a corresponding setup multicycle
assignment.
The multicycle_consistency check reports all the multicycle cases where a setup multicycle does not equal
one greater than the hold multicycle. Hold multicycle assignments are usually one cycle less than setup
multicycle assignments.
The partial_min_max_delay check verifies that each minimum delay assignment has a corresponding
maximum delay assignment, and vica versa.
The clock_assignments_on_output_ports check reports all the clock assignments that have been applied to
output ports.
The input_delay_assigned_to_clock check verifies that no input delay value is set for a clock. Input delays
set on clock ports are ignored because clock-as-data analysis takes precedence.
The generated_io_delay check reports all the IO delays that have no specifications for -reference_pin,
-clock (generated clocks), or -source_latency_included.
Example
# Constrain design
create_clock -name clk -period 4.000 -waveform { 0.000 2.000 } \
[get_ports clk]
set_input_delay -clock clk2 1.5 [get_ports in*]
set_output_delay -clock clk 1.6 [get_ports out*]
set_false_path -from [get_keepers in] -through [get_nets r1] -to \
[get_keepers out]
# Check if there were any problems
check_timing -include {loops latches no_input_delay partial_input_delay}