Family=<device family, Generate_cmp_file=<design file, Generate_functional_sim_netlist – Altera Quartus II Scripting User Manual

Page 73: Generate_inc_file=<design file, Generate_inst_file=<design file, Generate_symbol=<design file, Ignore_carry_buffers[=on|off, Ignore_cascade_buffers[=on|off

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Chapter 2: Command-line Executables

2–47

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© July 2013

Altera Corporation

Quartus II Scripting Reference Manual

--family=<device family>

Option to target the specified device family. If the "--part" option is not used, the part is set to Auto.

The family name should not contain any spaces, for example, --family=APEXII. If you need to add space
between words in the family name, make sure that you enclose the words in double quotation marks "", for
example, --family="APEX II".

--generate_cmp_file=<design file>

Option to create a default VHDL Component File (.cmp) that represents the entities in the specified Text
Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design
File (.bdf), CusP file (.cpp) and MATLAB File (.mdl).

--generate_functional_sim_netlist

Option to prepare the databases necessary for functional simulation.

--generate_inc_file=<design file>

Option to create a default AHDL Include File (.inc) that represents the entities in the specified Text Design
File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design File
(.bdf).

--generate_inst_file=<design file>

Option to create a default Verilog Instantiation File (.inst) that represents the entities in the specified Text
Design File (.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), Block Design
File (.bdf), CusP file (.cpp) or MATLAB file (.mdl).

--generate_symbol=<design file>

Option to create a Block Symbol File (.bsf) that represents the entities in the specified Text Design File
(.tdf), VHDL Design File (.vhd), Verilog Design File (.v), EDIF Input File (.edf), or Block Design File (.bdf).

--ignore_carry_buffers[=on|off]

Option to ignore CARRY_SUM buffers that are instantiated in the design. (This option also applies to
MAX+PLUS II-style CARRY buffers.)

--ignore_cascade_buffers[=on|off]

Option to ignore CASCADE buffers that are instantiated in the design.

--incremental_compilation=<off|full_incremental_compilation>

Option to specify the incremental compilation mode.

The following table displays available values:

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