Altera Quartus II Scripting - Manual (Page 71)

Chapter 2: Command-line Executables 2–45
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© July 2013 Altera Corporation Quartus II Scripting Reference Manual
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Quartus ® II Analysis & Synthesis builds a single project database that integrates all the design files in a
design entity or project hierarchy. Analysis & Synthesis includes Quartus II Integrated Synthesis, which
provides comprehensive Verilog HDL and VHDL language support, as well as support for Altera-specific
languages such as AHDL.
Usage
quartus_map [-h | --help[=<option|topic>] | -v]
quartus_map <project name> [<options>]
This command supports the following options:
Option Page
-c=<revision name> ............................................................................................................................... 2–96
-f=<argument file>................................................................................................................................. 2–92
-h............................................................................................................................................................... 2–92
-l=<path>................................................................................................................................................. 2–46
-v ............................................................................................................................................................... 2–92
--64bit ....................................................................................................................................................... 2–92
--analysis_and_elaboration................................................................................................................... 2–46
--analyze_file=<design file> ................................................................................................................. 2–46
--convert_bdf_to_verilog=<.bdf file>.................................................................................................. 2–46
--convert_bdf_to_vhdl=<.bdf file> ...................................................................................................... 2–46
--effort=<auto|fast> .............................................................................................................................. 2–46
--enable_wysiwyg_resynthesis[=on|off] ........................................................................................... 2–46
--family=<device family> ..................................................................................................................... 2–47
--generate_cmp_file=<design file>...................................................................................................... 2–47
--generate_functional_sim_netlist ....................................................................................................... 2–47
--generate_inc_file=<design file> ........................................................................................................ 2–47
--generate_inst_file=<design file> ....................................................................................................... 2–47
--generate_symbol=<design file> ........................................................................................................ 2–47
--help[=<option|topic>] ....................................................................................................................... 2–93
--ignore_carry_buffers[=on|off] .......................................................................................................... 2–47
--ignore_cascade_buffers[=on|off] ..................................................................................................... 2–47
--incremental_compilation=<off|full_incremental_compilation>................................................. 2–47
--lib_path=<path> .................................................................................................................................. 2–48
--lower_priority ...................................................................................................................................... 2–93
--optimize=<area|speed|balanced> .................................................................................................. 2–48
--parallel[=on|off].................................................................................................................................. 2–48
--part=<device>...................................................................................................................................... 2–48
--partition=<NONE>............................................................................................................................. 2–48
--rev=<revision name>.......................................................................................................................... 2–96
--set=<assignment=value> ................................................................................................................... 2–96
--source=<source file>........................................................................................................................... 2–49
--state_machine_encoding=<auto|minimal_bits|one_hot|user_encoded>................................ 2–49
--update_wysiwyg_parameters ........................................................................................................... 2–49
--verilog_macro=<NONE>................................................................................................................... 2–49
--version................................................................................................................................................... 2–93