Resolve_file_path, Usage, Options – Altera Quartus II Scripting User Manual

Page 363: Description, Example, Resolve_file_path –233

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Chapter 3: Tcl Packages & Commands

3–233

project

© July 2013

Altera Corporation

Quartus II Scripting Reference Manual

resolve_file_path

Usage

resolve_file_path <file_name>

Options

<file_name>: Option to specify the file name

Description

Returns the resolved full path of the specified file name. If the file does not exist, the original file name is
returned.

The Quartus II software resolves relative paths by searching for the file in the following directories in the
following order:

1) Project directory, which is the directory where the Quartus II Settings File (.qsf) is found.
2) Project database directory, which is the "db" directory found under the project directory.
3) Project library directories, which are the directories containing the user-specified libraries that are used
only by the current project.
4) User library directories, which are the directories containing the user-specified libraries that are
used by all Quartus II projects.
5) Quartus II library directory, which is the directory containing Quartus II libraries.

Example

project_new chiptrip -overwrite

# Set one Verilog source file assignment
set_global_assignment -name VERILOG_FILE chiptrip.v

# Display the resolved full path of the Verilog
# source file assignment
set filename [get_global_assignment -name VERILOG_FILE]
set resolved_fullpath [resolve_file_path $filename]

puts "Full Path: $resolved_fullpath"

# Set more Verilog source file assignments
set_global_assignment -name VERILOG_FILE auto_max.v
set_global_assignment -name VERILOG_FILE speed_ch.v
set_global_assignment -name VERILOG_FILE tick_cnt.v
set_global_assignment -name VERILOG_FILE time_cnt.v

# Display the resolved full path of all the Verilog
# source file assignments
set file_asgns [get_all_global_assignments -name VERILOG_FILE]
foreach_in_collection file_asgn $file_asgns {

## Each element in the collection has the following
## format: {} {VERILOG_FILE} {<file_name>}

set filename [lindex $file_asgn 2]
set resolved_fullpath [resolve_file_path $filename]

puts "Full Path: $resolved_fullpath"
}

project_close

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