Altera Quartus II Scripting - Manual (Page 131)

© July 2013 Altera Corporation Quartus II Scripting Reference Manual
3. Tcl Packages & Commands
Command Name Package Page
add_new_cell chip_planner 3–35
add_new_io chip_planner 3–36
add_row_to_table report 3–248
add_to_collection sta 3–376
add_usage chip_planner 3–37
all_clocks sdc 3–283
all_inputs sdc 3–284
all_outputs sdc 3–285
all_registers sdc 3–286
apply_command chip_planner 3–38
assignment_group project 3–186
auto_partition_design incremental_compilation 3–105
begin_logic_analyzer_interface_control logic_analyzer_interface 3–161
begin_memory_edit insystem_memory_edit 3–125
change_bank_to_output_pin logic_analyzer_interface 3–162
check_netlist_and_save chip_planner 3–39
check_node chip_planner 3–40
check_timing sta 3–377
checksum misc 3–167
close_chip_planner chip_planner 3–41
close_device jtag 3–145
close_session stp 3–468
compare_vector simulator 3–346
compute_pll iptclgen 3–140
compute_slack_on_edges timing 3–475
connect_chain chip_planner 3–42
convert_signal_probes chip_planner 3–43
convert_vector simulator 3–350
create_base_clock timing_assignment 3–485
create_clock sdc 3–287
create_generated_clock sdc 3–288
create_migrated_script chip_planner 3–44
create_p2p_delays advanced_timing 3–12
create_partition incremental_compilation 3–107
create_relative_clock timing_assignment 3–487