Altera Quartus II Scripting - Manual (Page 162)

3–32 Chapter 3: Tcl Packages & Commands
backannotate
Quartus II Scripting Reference Manual © July 2013 Altera Corporation
Altera recommends that you use a Verilog Quartus®Mapping File (.vqm) as the source. When any of the
advanced netlist optimizations are enabled, it is possible for the Fitter to create and rename nodes in the
design during a place and route operation. Back annotation requires that on subsequent compilations the
node names in the netlist match those in the constraint file. Write out a VQM netlist and create a new
project using that netlist as its source. Copy all of the existing constraint files into the new project directory
and remove all the design files except the new .vqm by using the Add/Remove Files in a Project command
(Project menu) in the Quartus II GUI.
The Quartus II software will create a root region if you back-annotate nodes that are not members of a
LogicLock region. The root region is device-size and locked. You can make assignments to the root region
but you cannot delete it or modify its size or location.
Example
# Open the project "example_project"
project_open example_project
# Compile the design
package require ::quartus::flow
execute_flow -compile
package require ::quartus::backannotate
# Back annotate all nodes and routing in the region "one_region"
logiclock_back_annotate -routing -lock -no_demote_lab -region one_region
# Back annotate the location of the nodes on all paths that
# start with a node that matches the "Data_in*" wildcard
# expression, and end with a node that matches the "Data_out*"
# wildcard expression
logiclock_back_annotate -from Data_in* -to Data_out*
# Back annotate the placement of all the registers in the design
logiclock_back_annotate -resource_filter "REGISTER"
# Close the project
project_close
Keyword Resource Represented
COMBINATORIAL combinatorial nodes
REGISTER registered nodes
MEGA M-RAMs
MEDIUM M4K memory blocks
SMALL M512 memory blocks
IO I/O elements
MAC DSP blocks