Altera Quartus II Scripting - Manual (Page 450)

3–320 Chapter 3: Tcl Packages & Commands
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Quartus II Scripting Reference Manual © July 2013 Altera Corporation
If pin names or collections are used, the -from value must be a clock pin and the -to value must be any
non-clock input pin to a register. Assignments from clock pins or to and from cells applies to all registers in
the cell or driven by the clock pin.
The -through values are collections of pins or nets in the design. An exception applied through a node in
the design applies only to paths through the specified node.
The -rise_from and -fall_from options can be used in place of the "-from" destination nodes. The rise or fall
value of the option indicates that the "from" nodes are driven by the rising or falling edge of the clock that
feeds this node taking into consideration any logical inversions along the clock path. The "-from" option is
the combination of both rising and falling "from" nodes. If the "from" collection is a clock collection, the
assignment applies to those nodes that are driven by the respective rising or falling clock edge.
The -rise_to and -fall_to options behave similarly to the "from" options described previously. These
assignments restrict the given assignment to only those nodes or clocks that correspond to the specified
rise or fall value taking into consideration any logical inversions that are along the clock path.
The values of the -from, -to, -through, and similar options are either collections or a Tcl list of wildcards
used to create collections of appropriate types. The values used must follow standard Tcl or
TimeQuest-extension substitution rules. See help for the use_timequest_style_escaping command for
details.
Example
create_clock -period 10.000 -name CLK [get_ports clk]
create_generated_clock -divide_by 2 -source [get_ports clk] -name CLKDIV2 \
[get_registers clkdiv]
# Apply a source multicycle of 2 with a hold multicycle of 1 for all
# paths from the CLK domain to the CLKDIV2 domain.
set_multicycle_path -start -setup -from [get_clocks CLK] -to \
[get_clocks CLKDIV2] 2
set_multicycle_path -start -hold -from [get_clocks CLK] -to \
[get_clocks CLKDIV2] 1
# Apply a multicycle constraint of 3 (with a default hold multicycle of
# 0) for a
# specific path in the design.
set_multicycle_path -end -setup -from [get_pins rega|clk] -to \
[get_pins regb|*] 3
# Apply a multicycle constraint of 2 to a given cell, except for the
# reset pin.
set_multicycle_path -end -setup -to [get_cells regb] 2
set_multicycle_path -end -setup -to [get_pins regb|aclr] 1
#Apply a multicycle constraint of 3 rising from a clock and falling to a
# node
set_multicycle_path -end -setup -rise_from [get_clocks CLK] -fall_to \
[get_pins regb|datab] 3